1. Field of Invention
The present invention generally relates to semiconductor processing. More particularly, the present invention relates to reducing gate wrap around during manufacture of semiconductor devices.
2. Discussion of the Related Art
Insulated gate field effect transistors (“IGFETs”) have become the active electronic element of choice for the majority of digital electronic circuits formed at small size and high integration density. The basic principle of operation of field effect transistors is to use a voltage applied to a gate electrode insulated from the conduction channel of the device to develop an electric field which controls the population of carriers in a body of semiconductor material which forms the conduction channel of the device.
Trench isolation is an isolation technique developed especially for a semiconductor chip with high integration. The trench regions are formed in the semiconductor substrate by recessing the substrate deep enough for isolation and filling the recess with insulating material to provide the isolation among active devices or different well regions.
FIG. 1 illustrates how improper formation of isolation structures may lead to corner effects at the interface of the semiconductor substrate surface and trench, such as “gate wrap around” and “parasitic leakage.” A gate oxide layer 116 is formed above a substrate 100 in which isolation trenches are filled with a dielectric 108. A gate conductor layer 118 is formed over the active and field regions.
Parasitic leakage paths have been found because of the proximity of a transistor gate to an edge or corner of a trench. The parasitic leakage paths result from an enhancement of the gate electric field near the trench corner. The electric field is enhanced by the corner's small radius of curvature and the proximity of the gate conductor. Processing can exacerbate the problem by sharpening the corner and thinning the gate dielectric near the corner. In a worst case scenario for corner field enhancement, the gate layer wraps around the trench corner, resulting in so called “gate wrap around,” as shown by encircled area 101. This happens when the oxide fill in the isolation trench is recessed below the silicon surface during subsequent etch processing.
Accordingly, the electrical field developed within the conduction channel may not be uniform, particularly at the lateral edges or corners of the conduction channel (which generally coincides with the intersection of the trench and the surface of the semiconductor substrate). The conduction characteristics at the corners of the channel may therefore be quite different from those of the central portion of the channel. In relatively larger (i.e., wider channel) devices, the electric field can be considered as relatively uniform throughout the conduction channel as the planar or channel portion of the transistor generally dominates the on-current characteristics of the transistor. Consequently, device characteristics, such as threshold voltage (Vt), of particular interest in digital circuits, are highly predictable and controllable. However, as field effect transistors are made smaller (i.e., devices have a narrower channel), the conduction effects at the corners of the conduction channel become relatively more significant and, in fact, may dominate at sub-micron channel widths. The practical effect of corner conduction is to lower the threshold voltage of the transistor. Additionally, an increased variance in threshold voltage has been observed as device size decreases in the sub-micron regime where very small differences in channel dimensions may greatly affect the relative contributions of corner and channel conduction of transistors.
A scheme for controlling the corner area or edge of a trench is disclosed in U.S. Pat. No. 5,741,738 issued to Mandelman et al. A semiconductor substrate having a planar surface is provided. A trench having a sidewall is provided in the substrate, an intersection of the trench and the surface forming a corner. A dielectric lines the sidewall of the trench and a spacer is self-aligned to the edge of the trench dielectric to protect the corner during subsequent etches, preventing divoting and gate wrap around. However, Mandelman et al. disclose at least a portion of the spacer remains in place after subsequent etches. Disadvantageously, such a method and structure result in less area for the transistor channel per total area, where the total area includes the active area and the trench area.
Therefore, a method and structure to control threshold voltage by preventing corner parasitic conduction and gate wrap around is highly desirable.